A SoC Interconnexion Scheduling-Design and ...

A SoC (System-on-Chip) interconnection requires crossbar switches to connect inputs to outputs. These devices must be configured by a scheduling algorithm that allows arriving packets to be delivered across the switch efficiently and quickly. A suitable scheduling algorithm has to achieve the maximum throughput while maintaining stability and eliminating starvation. Thus, in this paper, we present a design and an implementation of a scheduler for a 32x32 SoC interconnexion based on an iterative scheduling algorithm that we called Credited-iSLIP (iterative Serial Line Internet Protocol). It is a variation of the iSLIP algorithm. A description of the scheduler designed is presented with simulation results to indicate its performance. The design has been implemented in VHDL RTL, simulated with Modelsim 6.2 and synthesized using Xilinx-ISE and the Virtex-4 device XC4VFX100-12FFG1517 of 90 nm technology to achieve a maximum frequency of 265.88 MHz, a minimum slices utilization of 771 and total estimated power consumption about 915 mW. The number of iterations is fixed to i = 8.